Method and apparatus for a high density magnetic random access memory (mram) with stackable architecture

ABSTRACT

The invention comprises a magnetic random access memory (MRAM) with stackable architecture. A first word line is configured to carry electric current. A first memory column is electrically coupled to the word line and is comprised of a plurality of memory cells electrically coupled and adjacent to each other. Each memory cell is configured to store data by magnetic alignment of the memory cell. A first bit line column is electrically isolated from the first word line and is magnetically coupled to and electrically isolated from the first memory column. The first bit line column comprises a plurality of bit lines that are electrically isolated from each other and configured to carry electric current during a memory read and a memory write. The first bit line column is parallel to the first memory column.

CROSS-REFERENCES TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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REFERENCE TO A “SEQUENTIAL LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISC (SEE 37 CFR 1.52(E)(5))

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to magnetic random access memory (MRAM).Specifically, the invention relates to a high-density memoryarchitecture comprising a vertical stack of magnetic storage elements.

DESCRIPTION OF THE RELATED ART INCLUDING INFORMATION DISCLOSED UNDER 37CFR 1.97 AND 1.98

MRAM devices typically consist of a planar arrangement of memory cellswith two magnetic layers separated by a tunnel junction. One of themagnetic layers is a fixed reference layer while the other layer is astorage layer having a magnetic polarization that is altered forstorage. The storage layer can be oriented along one of two directionsalong a magnetic uni-axial anisotropy axis approximately parallel oranti-parallel to the magnetization of the reference layer.

A memory write to a memory cell aligns the storage layer in either theparallel or the anti-parallel position with respect to the referencelayer. A memory read determines the resistance of the memory cell beingread and determines the alignment of the storage layer based on theresistance of the memory cell. Then the “value” of the memory cell isknown.

One problem with the prior art is that it is difficult to manufactureMRAM cells and they require a significant amount of space, thereforeyielding a low MRAM density. Furthermore, memory write requires a narrowdistribution of switching fields in order to avoid writing of halfselected bits or writing adjacent bits due to crosstalk. Memory read isusually performed by comparing the resistance of the cell being read toa reference cell, again requiring a relatively tight tolerances of cellresistance values across the memory chip. MRAM are therefore difficultto manufacture and have low density.

What is needed is high-density MRAM that is easy to manufacture andprovides good selectivity of memory cells. The invention should reducethe area required by memory, be easily manufactured by lowering themargin requirements for memory resistance, provide improved selectivityof memory cells, and be scalable.

SUMMARY OF THE INVENTION

The invention comprises a magnetic random access memory (MRAM) withstackable architecture. A first word line is configured to carryelectrical current. A first memory column is electrically coupled to theword line and is comprised of a plurality of memory cells electricallycoupled and adjacent to each other. Each memory cell is configured tostore data by magnetic alignment of the memory cell. A first bit linecolumn is electrically isolated from the first word line and ismagnetically coupled to and electrically isolated from the first memorycolumn. The first bit line column comprises a plurality of bit linesthat are electrically isolated from each other and configured to carryelectrical current during a memory read and a memory write. The firstbit line column is parallel to the first memory column.

The advantages of the invention include a reduced MRAM area achieved byreducing the number of word lines, reducing the number of switches (forexample, transistors and diodes) per memory cell and improving thegeometry of the bit line/memory cell relationship, improved simplicityin the manufacturing process, improved selectivity, and increased memorydensity. For example, the invention may apply an eight-layer design witha cell size of only 1 F2.

BRIEF DESCRIPTION OF THE DRAWING(S)

FIG. 1 is a schematic illustrating a cross section of one embodiment ofthe invention.

FIG. 2 is a schematic illustrating a plan view of one embodiment of theinvention from FIG. 1.

FIG. 3 is a diagram illustrating one embodiment of the invention without-of-plane magnetization.

FIG. 4 is a diagram illustrating bit lines, magnetic fields and a memorycell.

FIG. 5 is a diagram illustrating the storage and readout layers of amemory cell.

FIG. 6 is a diagram illustrating one embodiment of the invention within-plane magnetization.

FIG. 7 is a diagram illustrating a sensor bit line making and processflow for the invention.

FIG. 8 is a flow diagram illustrating one method of executing memorywrite.

FIG. 9 is a flow diagram illustrating one method of executing memoryread.

DETAILED DESCRIPTION OF THE INVENTION

The layering processes and materials used in the following magneticmemory cells are well known in the material processing art. Althoughspecific embodiments have been described, one of ordinary skill in theart will recognize that other materials and other layering processesthan those described may be used in accordance with the invention.

FIG. 1 is a schematic illustrating a cross section of one embodiment ofMRAM 100. MRAM 100 includes electrically conducting word line 102connected to memory columns 104. Each memory column 104 consists of oneor more memory cells 106 stacked on top of each other and electricallyconnected.

Memory cell 106 is a magnetic tunnel junction (MTJ) composed of twolayers: a storage layer and a readout layer. Both layers are magneticwith either in-plane magnetization or out-of-plane magnetization. Thestorage layer has a higher coercivity than the readout layer. Layerswith in-plane magnetization may be made with, for example, approximatelyNi₈₀Fe₂₀, Co, or CoFe alloys. Layers made with out-of-planemagnetization may be made with, for example, Co/Pt multilayers orRare-Earth Transition Metal alloys. Although four memory cells 106 areillustrated in each memory column 104, fewer or more memory cells may beincluded.

Switch 108 is opposite word line 102 on memory column 104. Switch 108turns on one or more of memory columns 104 during an operation. Wordline 102 carries electrical current that flows through, for example,memory column 104-1 when switch 108-1 is activated. One aspect of theinvention is that only one switch 108 is needed for multiple memorycells 106. In one embodiment, switches 108 are transistors. In the priorart, each memory cell typically has one transistor per memory cell.

Bit line columns 110 are positioned alongside memory columns 104.Although FIG. 1 illustrates a bit line column between each memorycolumn, one skilled in the art will recognize that fewer bit linecolumns may be used in the invention. Bit line columns include bit lines112. Bit lines 112 are conductors that carry electric current in orderto generate a magnetic field that switches the polarity of the storageand readout layers in memory cells 106. Positioning bit lines 112 on thesides of memory cells 110 reduces masking layers and process stepsduring memory fabrication. The invention is applicable to both 1T1MTJand 1D1MTJ architecture to achieve 1TnMTJ and 1DnMTJ respectively.

In one embodiment, MRAM 100 is fabricated on a substrate which conta.

ins transistors 108 for addressing memory columns 104 and peripheralcircuitry providing power, sensing, address registers, etc. (not shown).A silicon wafer may be used as a substrate, however, other materialswith appropriate electrical and thermal properties may also be used as asubstrate. The substrate must be such that the address transistor 108and all the peripheral electronics can be built in it. It should havesufficient thermal conductivity to dissipate the heat produced by theMRAM cells. Other materials include SiO, SiC, polySi.

FIG. 2 is a schematic illustrating a plan view of one embodiment of theinvention from FIG. 1. MRAM 200 has word lines 210 connected to memorycolumns 220. Bit lines 230 are perpendicular to word lines 210 andstacked as illustrated in FIG. 1. Each word line 210 activates severalmemory columns 220, according to the design and architecture of MRAM200.

FIG. 3 is a cross-sectional diagram illustrating one embodiment of theinvention with out-of-plane magnetization. MRAM 300 includes word line305 connected to memory columns 310 with memory cells 315. Connectedopposite word line 305 are switches 320. Bit line columns 325 includebit lines 330.

In one embodiment, memory cells 315 and bit lines 330 in MRAM 300 arecomposed of several layers. Element 340 illustrates the layers. Layers345 may include Ni₈₀Fe₂₀ that is approximately 30 nm thick. Top andbottom NiFe layers 345 may be included as cladding layers to avoidleakage of magnetic field above and below the bit lines when activated.One purpose of layers 345 is to concentrate the flux on either side ofthe bit lines 330, rather than above and below.

Layer 350 is a multilayer of (CuTa), shown as 4 repeating layers in 340,which may be included to adjust the conductivity of bit lines 330. TheCu and Ta of each layer may be 10 nm and 5 nm thick respectively.

Layer 355 is a multilayer (4 repeats) of (CoPt), which is the storagelayer with higher coercivity (harder) than the readout layer. The Co maybe approximately 0.5 nm thick and the Pt may be approximately 2 nmthick.

Layer 360 is a multilayer (2 repeats) of (PtCo), which is the readoutlayer with lower coercivity (softer) than the storage layer. The Co maybe approximately 0.5 nm thick and the Pt may be approximately 2 nmthick. In CoPt multilayers, the coercive field can be adjusted byvarying the thickness of the layers and number of repeats. Generally,the coercive field increases with the number of repeats. One example ofvalues of the coercive field for the readout and storage layers is 20 Oefor the readout layer and 60 Oe for the storage layer. The magneticpolarization of both the readout and storage layers are aligned during amemory write, while the magnetic polarization of only the readout layeris switched during a memory read.

Layer 365 is Al₂O₃, which is an insulating layer that forms a tunnelbarrier between layers 355 and 360. The Al₂O₃ may be approximately 1 nmthick. Layer 365 may be formed, for example, by depositing about 0.8 nmof metallic aluminum and oxidizing it with plasma or natural oxidation.The other layers in element 340 may be deposited by sputtering. Elements340 making up memory cells 315 may be connected by copper, aluminum, orother conductors. Elements 340 making up bit lines 330 may be connectedby insulators, for example SiO₂, Al₂O₃, or other oxides. One skilled inthe art will recognize that memory cells 315 and bit lines 330 need notbe fabricated in the same way or with the same material as each other,however manufacturing is simplified if they are the same.

For out-of-plane magnetization, the magnetic storage and readout layersmay be made from Co/Pt multilayers, CoFeNi/Pt multilayers, Co/Pt alloys,Co/Pd multilayers, Co/Pd alloys, CoFeNi/Pd multilayers, Co/Aumultilayers, CoFeNi/Au multilayers, Co/Ni multilayers, Ni/Cu multilayersor rare earth-transition metal alloys. If heating is used as a selectmethod (see below), the storage layer can be exchange biased with anantiferromagnetic layer with low blocking temperature, for exampleIr₂₀Mn₈₀ with a thickness of 6 nm.

Layer 370 between the memory cells may be formed from vapor-deposited orsputtered Cu, which facilitates current transmission through the memorycolumns. Layer 370 is approximately 100-300 nm thick. The thickness oflayer 370 may vary according to selectivity desired between the memorycells. Greater space between memory cells will help selectivity using asingle bit line, while less space between memory cells is needed whenusing two bit lines for selection. Although the various layers have aspecific purpose for memory cells, they are not as relevant in the bitlines, where storage does not occur. Rather, bit lines should containmaterial that will carry current in order to select the memory cells.Layering the bit lines with the same material as the memory cellssimplifies manufacturing of the MRAM.

FIG. 4 is a diagram illustrating bit lines, magnetic fields and a memorycell. One method for performing a memory write, or storing data withinMRAM 300 for out-of-plane magnetization, follows for memory cell 400. Amemory write operation for in-plane magnetization differs and will bedescribed below. Electric current flowing in opposite directions is feedto bit lines 410 and 420. Current in bit line 410 flows perpendicularand into the plane of FIG. 4 while current in bit line 420 flowsperpendicular and out of the plane of FIG. 2. Because the current is inopposite directions, the magnetic field around each of bit lines 410 and420 are in opposite directions. The magnetic field around bit line 410is clockwise while the magnetic field around bit line 420 is counterclockwise.

Memory cell 400 is selected by powering the associated word line andselecting the memory column to which memory cell 400 belongs by turningon the appropriate switch.

Current flowing through a memory cell reduces the switching field by oneof several effects. First, thermal heating of the storage layer due tocurrent flowing through the tunnel barrier causes the switching field todecrease. Heating of memory cell 400 makes it possible to align themagnetic polarity in the storage and readout layers with the cumulativeeffect of magnetic fields around bit lines 410 and 420. Pulses ofcurrent through bit lines 410 and 420 can be adjusted so that only theheated junction switches, rather than other memory cells which are at astandby temperature.

Furthermore, the Oersted field due to the vertical current flow throughthe memory column of memory cell 400 reduces the switching field becauseit favors the formation of an in-plane vortex state that, due tocylindrical symmetry, helps the reversal of magnetization.

Finally, injection of spin-polarized electrons from the readout layer orfrom a polarizing additional layer into the storage layer can be used todecrease the switching field of the storage layer magnetization.

Memory cell 400 must be far enough from bit lines 410 and 420 so thatcurrent through bit lines 410 and 420 does not leak into memory cell400, and close enough for a magnetic field around bit lines 410 and 420to affect the magnetic polarity of memory cell 400. In one embodiment,memory cell 400 is approximately 100 nm from bit line 410. Typically,current through bit lines 410 and 420 (and word lines, see FIG. 1)ranges from 1-5 mA. One skilled in the art will recognize that distancesbetween memory cells and bit lines changes relative to the state of theart and is not a limiting factor of the invention. Decreasing thedistance between memory cells increases the density, which is usually agoal in memory design. Also, current levels may differ depending on theparticular application.

FIG. 5 is a diagram illustrating the storage and readout layers of amemory cell with out-of-plane magnetization. After a memory write,memory cell 500 has the magnetic polarization for both readout layer 510and storage layer 520 aligned in the same direction. Readout layer 510is separated from storage layer 520 by dielectric layer 530, whichcreates a tunnel junction between readout layer 510 and storage layer520. Although FIG. 5 illustrates the readout layer on top, either thereadout layer or the storage layer may be on top or bottom. Also,storage values of “1” and “0” may be arbitrarily assigned to storagelayer 520 being in the up (parallel) and down (anti-parallel) position.

One method a performing a memory read, or retrieving data from a memorycell, follows for memory cell 106-2, assuming out-of-planemagnetization. One problem with connecting multiple memory cells betweena single word line and a transistor is that it is more difficult todetect the resistance of individual memory cells and therefore thepolarization of the storage layer within the memory cell. The inventionovercomes this difficulty with differential readout.

In a manner similar to memory write, counter-directed current flowsthrough each of bit lines 112-1 and 112-2 (also see FIG. 4). Thestrength of the magnetic field through memory cell 106-2 (also see 400)is directly related to the strength of current through bit line 112-1and 112-2 (also see 410 and 420). A magnetic field through memory cell106-2 (also see 400) is made strong enough to switch readout layer 510(see FIG. 5), which has lower coercivity than storage layer 520 and istherefore easier to switch its magnetic polarity, but weak enough not toswitch storage layer 520. Whether magnetic polarization in readout layer510 actually switches is irrelevant; rather, it enters a predeterminedstate based on current flow through bit lines 112-1 and 112-2 (also see410 and 420).

The resistance of memory column 104-1 is then determined by well knowmethods. Then, the direction of current through bit lines 112-1 and112-2 is switched and the respective magnetic fields switch alignment ofthe magnetic polarization for readout layer 510, again without switchingstorage layer 520. Resistance of memory column 104-1 is againdetermined. Based on the difference in resistance between the firstreading and the second, and the known magnetic polarization of readoutlayer 510 during the first and second reading, the magnetic polarizationof storage layer 320 becomes known. Resistance through a memory cell islower when both the storage layer and readout layer are aligned in thesame direction, higher when they are aligned in opposite directions.

For example, if readout layer 510 is first aligned in the up directionand then in the down direction, and the resistance during the secondreading increases, then storage layer 520 is aligned in the up direction(parallel). Conversely, if readout layer 510 is first aligned in the updirection and then in the down direction, and the resistance during thesecond reading decreases, then storage layer 520 is aligned in the downdirection (anti-parallel). Although a two-part memory read may requiremore time than a one-part memory read, when used in a NAND mode thestackable arrangement simplifies the read process and improvesperformance.

There are two commonly used architectures in non-volatile memory cells:NOR and NAND. In the NOR architecture, each bit cell is individuallyaddressed by a separate word line and a separate bit line. In the NANDarchitecture several memory cells are connected in series to one commonword line, for example. The common word line remains in the “on” statewhile the individual bit lines address each of the connected cells. NORarchitectures are often used for programming while NAND memories aretypically used for storage applications. The stackable architecturedescribed here lends itself to be used in an NAND configuration.

In another embodiment, the readout layer is biased (with an exchangelayer for example) so that the standby direction of its magnetization isalways fixed, for example in the upward direction. The readout schemethen involves applying a pulse of opposite currents in the adjacent bitlines to temporarily switch the magnetization of the readout layer inthe downward direction (without switching the storage layer) and measurethe resulting voltage across the memory stack. If the pulse correspondsto a temporary increase in resistance of the stack, the storage layer ismagnetized in the up direction. Conversely, if the pulse corresponds totemporary decrease in the resistance of the stack, the storage layer ismagnetized in the down direction. In this embodiment, the read processconsists of only one step to determine the state of magnetization of thestorage layer.

In another embodiment, selectivity of the memory cell is achieved withcurrent running through a single bit line, rather than both bit lines.One skilled in the art will recognize that the invention encompasses theposition of the bit lines with respect to the memory cell and word line.Two bit lines carrying current improves selectivity, but is notnecessary to practice the invention. This is applicable to both memoryread and memory write.

FIG. 6 is a cross-sectional diagram illustrating one embodiment of theinvention with in-plane magnetization. MRAM 600 includes word line 605connected to memory columns 610 with memory cells 615. Connectedopposite word line 605 are switches 620. Bit line columns 625 includebit lines 630.

In one embodiment, memory cells 615 and bit lines 630 in MRAM 600 arecomposed of several layers, described below. Element 640 illustrates thelayers. Layer 645 may include a multilayer of (Cu/Ta) (4 repeats) withthe Cu approximately 10 nm thick and the Ta approximately 3 nm thick.Layer 645 may be used to adjust the conductivity of the bit lines to theappropriate value, which depends on the length and width of the line.The resistance of layer 645 will not greatly affect the MTJ because thetunnel barrier has a much greater resistance.

Layer 650 is a crystalline lattice of Ir₂₀Mn₈₀, with the IrMnapproximately 5 nm thick. Layer 655 is Co₉₀Fe₁₀, which together withIrMn (layer 650) constitutes the storage layer. Layer 655 isapproximately 10-50 nm thick.

Layer 660 is Al₂O₃ with a thickness of approximately 1.2 nm. Layer 660forms the tunnel barrier between the storage and readout layers. Layer660 may be formed, for example, by depositing about 0.8 nm of metallicaluminum and oxidizing it with plasma or natural oxidation. The otherlayers in element 640 may be deposited by sputtering.

Layer 670 is Ni₈₀Fe₂₀ that is approximately 25 nm thick. Layer 670 formsa free layer that is magnetostatically coupled parallel to themagnetization of the top NiFe layers of the adjacent bit lines.

Elements 640 making up bit lines 630 may be connected by insulators, forexample SiO₂, Al₂O₃, or other oxides. One skilled in the art willrecognize that memory cells 615 and bit lines 630 need not be fabricatedin the same way or with the same material as each other, howevermanufacturing is simplified if they are the same.

Layer 680 between the memory cells is Cu, which facilitates currenttransmission through the memory columns. Although the various layershave a specific purpose for memory cells, they are not as relevant inthe bit lines, where storage does not occur. Rather, bit lines shouldcontain material that will carry current in order to select the memorycells. Layering the bit lines with the same material as the memory cellssimplifies manufacturing of the MRAM.

One method of performing a memory write, or storing data within MRAM 600for out-of-plane magnetization, follows for memory cell 615. Electriccurrent flowing (or pulsed) in the same direction is feed to bit lines630-1 and 630-2. Current in bit lines 630-1 and 630-2 is shown flowingperpendicular and into the plane of FIG. 6. Layer 670 on each of bitlines 630-1 and 630-2 act as cladding layers. Layers 670 are polarizedin an Oersted magnetic field generated by the current through bit lines630-1 and 630-2. Due to the parallel magnetostatic coupling betweenthese layers 670 on bit lines 630-1 and 630-2, and layer 670 on memorycell 615, the magnetization of layer 670 in memory cell 615 alignsparallel to the magnetic field of bit lines 630-1 and 630-2.

In order to select memory cell 615, current flows through word line 605,memory column 610-1, and switch 620-1. Then, because of anti-parallelmagnetostatic coupling with the storage layer, the storage layerswitches in the anti-parallel direction.

Current flowing through a memory cell reduces the switching field by oneof several effects. First, thermal heating of the storage layer due tocurrent flowing through the tunnel barrier causes the switching field todecrease. If the current is large enough the storage layer is heatedabove its blocking temperature. In Ir₂₀Mn₈₀, it is known that theblocking temperature can be adjusted from 150C to 300C by varying thethickness of this layer. The Co magnetization becomes anti-parallel tothe NiFe layer and freezes in this direction when the temperaturedecreases back to the standby temperature. Therefore, the direction ofmagnetic field created by the pulses of current in the bit linesdetermines the alignment of the magnetization of the storage layer.

Furthermore, the Oersted field due to the vertical current flow throughthe memory column of the memory cell reduces the switching field becauseit favors the formation of an in-plane vortex state that, due tocylindrical symmetry, helps the reversal of magnetization. In oneembodiment, the storage layer is made with CO₅₀Fe₅₀, or of a CoFe/IrMnbilayer with reduced IrMn thickness, for example 4 nm, so that thestorage layer will have greater coercivity but no loop shift.

Finally, injection of spin-polarized electrons from the readout layer orfrom a polarizing additional layer into the storage layer can be used todecrease the switching field of the storage layer magnetization.

A memory read for in-plane magnetization operates in the same manner asfor out-of-plane magnetization, with the exception that current carriedthrough the bit lines travels in the same direction, rather than inopposite directions, during the initial setting of the readout layer andthe switching of the readout layer.

In another embodiment, selectivity of the memory cell is achieved withcurrent running through a single bit line, rather than both bit lines.One skilled in the art will recognize that the invention encompasses theposition of the bit lines with respect to the memory cell and word line.Two bit lines carrying current improves selectivity, but is notnecessary to practice the invention. This is applicable to both memoryread and memory write.

FIG. 7 is a diagram illustrating the making and process flow for theinvention. In block 700, start with planarized dielectric surface 705with an embedded conductor pad to connect to the memory cell. In block710, deposit buffer/sensor/conductor stack 715 and spin coat photoresist720. In block 725, expose and develop memory cell and bit line pattern730. In block 735, etch with an ion beam through sensor stack 740, fillwith dielectric 740, and lift off photo-resist. In block 750, planarizebuffer 755, blank deposit a dielectric, and spin resist, expose anddevelop conductor pad for the next conductor stack by photoresist. Inblock 760, etch to the buffer, remove resist, blank deposit conductor765, planarize to dielectric 770, and remove resist. This methodrequires only two photomasking plus one planarization per sensor layer.

FIG. 8 is a flow diagram illustrating one method of executing memorywrite to a MRAM with a word line, a memory cell electrically coupled tothe word line, and a bit line coupled to, adjacent to and electricallyisolated from the memory cell. In block 800, generate an electriccurrent in the word line. In block 810, receive an electric current inthe memory cell. In block 820, generate a magnetic field around the bitline. In block 830, align a magnetic polarization within a readout layerin the memory cell according to the direction of the magnetic field. Inblock 840, align a magnetic polarization within a storage layeraccording to the direction of the magnetic field, the storage layercoupled to the readout layer and having a higher coercivity than thereadout layer.

FIG. 9 is a flow diagram illustrating one method of executing memoryread in a MRAM with a word line, a memory cell electrically coupled tothe word line, and a bit line coupled to, adjacent to and electricallyisolated from the memory cell. In block 900, generate a magnetic fieldaround the bit line. In block 910, generate an electric current in theword line. In block 920, receive an electric current in the memory cell.In block 930, align a magnetic polarization within a readout layer inthe memory cell according to the direction of the magnetic field. Inblock 940, measure a resistance of the memory cell. In block 950,reverse the magnetic field around the bit line. In block 960, reversethe magnetic polarization within the readout layer. In block 970,measure the resistance of the memory cell.

The advantages of the invention include a reduced MRAM cell areaachieved by the stackable architecture which reduces the number of wordlines, improves the geometry of the bit line/memory cell relationshipand uses only one transistor per memory stack rather one transistor percell. In addition, the readout process is simplified requiring only thedetermination of the polarity when changing the magnetic states of onecell. In contrast, the prior art compares the resistance of a cell to adistinct reference cell requiring a narrow distribution resistancevalues. The manufacturing process is simplified by the co-planarmetallization process of bit lines and storage cells as well as therepeated application of only 2 masks per layer. Other advantages includeimproved write selectivity by the use of two adjacent bit lines andincreased memory density. For example, the invention may apply aneight-layer design with a cell size of only 1 F2.

One of ordinary skill in the art will recognize that configurations ofdifferent materials may be used without straying from the invention. Theillustrated embodiments of the invention include, for exampletransistors, but one skilled in the art recognizes that these may beinterchanged and/or replaced by components with similar functionality,for example diodes, applying appropriate circuit rerouting.Additionally, certain combinations of elements have been disclosed incertain thicknesses or certain ratios. However one of ordinary skill inthe art will recognize that other ratios will work and other thicknessesmay be used, as well as other materials. The embodiments describedherein are meant to provide an enabling disclosure only and not meant aslimiting features of the invention. As any person skilled in the artwill recognize from the previous description and from the figures andclaims that modifications and changes can be made to the inventionwithout departing from the scope of the invention defined in thefollowing claims.

1. A magnetic random access memory (MRAM) comprising: a substrate; afirst memory cell column extending perpendicularly from the substrateand comprising a plurality of stacked magnetic memory cells electricallycoupled to each other, each magnetic memory cell configured to storedata; a first bit line column extending perpendicularly from thesubstrate and adjacent to but electrically isolated from the firstmemory cell column, the first bit line column comprising a plurality ofstacked conductive bit lines electrically isolated from each other, eachbit line in the first bit line column being associated with a memorycell in the adjacent memory cell column and positioned close enough toits associated memory cell such that an electric current passing througha bit line will produce a magnetic field affecting the memory cellassociated with that bit line; and a first conductive word lineelectrically coupled to the first memory cell column and electricallyisolated from the first bit line column.
 2. (canceled)
 3. The MRAM ofclaim 1 wherein the bit lines in the first bit line column are alignedparallel to one another and is perpendicular to the first memory cellcolumn.
 4. The MRAM of claim 1 further comprising: an electricalinsulator located between the first bit line column and the first memorycell column.
 5. The MRAM of claim 1, further comprising: a second bitline column extending perpendicularly from the substrate andelectrically isolated from the first conductive word line, the secondbit line column comprising a plurality of stacked conductive bit lineselectrically isolated from each other, the bit lines in the second bitline column being aligned parallel to one another and to the bit linesin the first bit line column, the first and second bit line columnsbeing located on opposite sides of the first memory cell column; and anelectrical insulator located between the second bit line column and thefirst memory cell column. 6-9. (canceled)
 10. The MRAM of claim 5further comprising: a second memory cell column extendingperpendicularly from the substrate and electrically coupled to the firstconductive word line and comprising a plurality of stacked magneticmemory cells electrically coupled to each other, each memory cellconfigured to store data, the second memory cell column being parallelto the first memory cell column and adjacent to the first bit linecolumn.
 11. The MRAM of claim 10 further comprising: a second conductiveword line parallel to the first conductive word line; and a third memorycell column extending perpendicularly from the substrate parallel to thefirst memory cell column and electrically coupled to the secondconductive word line and comprising a plurality of magnetic memory cellselectrically coupled to each other, each memory cell configured to storedata.
 12. (canceled)
 13. The MRAM of claim 11 wherein the third memorycell column is located between the first and second bit line columns.14. The MRAM of claim 11 wherein one of the plurality of memory cells inthe first memory cell column is configured to store data when electriccurrent flows through the first conductive word line into the firstmemory cell column and electric current flows through one of the bitlines in the second bit line column.
 15. The MRAM of claim 14 whereinone of the plurality of memory cells in the first memory cell column isfurther configured to store data when electric current flows through oneof the bit lines in the first bit line column.
 16. The MRAM of claim 15wherein the direction of current flowing through one of the bit lines inthe first bit line column is opposite the direction of current flowingthrough one of the bit lines in the second bit line column.
 17. The MRAMof claim 15 wherein the direction of current flowing through one of thebit lines in the first bit line column is the same as the direction ofcurrent flowing through one of the bit lines in the second bit linecolumn.
 18. The MRAM of claim 1, each of the memory cells in the firstmemory cell column further comprising: a readout layer configured tohave a magnetic polarization; and a storage layer coupled to the readoutlayer and configured to have a magnetic polarization, the storage layerhaving a higher coercivity than the readout layer.
 19. The MRAM of claim18, wherein the readout layer and the storage layer are configured toalign their magnetic polarizations with a magnetic field generated bythe electric current in one of the bit lines during memory write, andthe readout layer is configured to align its magnetic polarization witha magnetic field generated by the electric current in one of the bitlines during memory read.
 20. A magnetic random access memory (MRAM)comprising: a substrate; a word line configured to carry electriccurrent; a stack of magnetic memory cells extending perpendicularly fromthe substrate and electrically coupled to the word line, each memorycell configured to store data; and a stack of bit lines extendingperpendicularly from the substrate adjacent to the stack of memorycells, each bit line being magnetically coupled to an adjacentassociated magnetic memory cell and electrically isolated from the wordline, each bit line configured to set a magnetic polarization within itsadjacent associated magnetic memory cell during a memory write operationand to set a magnetic polarization within its adjacent associatedmagnetic memory cell during a memory read operation.
 21. The MRAM ofclaim 20 wherein each bit line is further configured to reverse amagnetic polarization within its adjacent associated magnetic memorycell during the memory read operation.
 22. A method of writing tomagnetic random access memory (MRAM) with a word line, a magnetic memorycell electrically coupled to the word line, a switch electricallycoupled to the memory cell, and a bit line magnetically coupled to,adjacent to and electrically isolated from the memory cell, the methodcomprising: generating an electric current in the word line; turning onthe switch to direct current from the word line through the memory cell;generating a magnetic field around the bit line while current from theword line is passing through the memory cell to thereby align a magneticpolarization within the magnetic memory cell according to the directionof the magnetic field.
 23. The method of claim 22 wherein generating amagnetic field around the bit line to thereby align a magneticpolarization within the magnetic memory cell comprises: aligning amagnetic polarization within a readout layer in the magnetic memory cellaccording to the direction of the magnetic field; and aligning amagnetic polarization within a storage layer in the magnetic memory cellaccording to the direction of the magnetic field, the storage layercoupled to the readout layer and having a higher coercivity than thereadout layer.
 24. The method of claim 23, further comprising:generating an electric current; and electrically lowering the switchingfield of the memory cell.
 25. The method of claim 23, furthercomprising: heating the memory cell; and lowering the switching field ofthe memory cell.
 26. The method of claim 23, further comprising:generating an electric current, and magnetically lowering the switchingfield of the memory cell.
 27. A method of reading from a magnetic randomaccess memory (MRAM) with a word line, a magnetic memory cellelectrically coupled to the word line, and a bit line magneticallycoupled to, adjacent to and electrically isolated from the magneticmemory cell, the method comprising: generating a magnetic field in afirst direction around the bit line to thereby align a magneticpolarization within the memory cell according to said first direction ofthe magnetic field; measuring a resistance of the memory cell;generating a magnetic field in a second direction opposite said firstdirection around the bit line to thereby reverse the magneticpolarization within the magnetic memory cell; and measuring theresistance of the magnetic memory cell with said reversed magneticpolarization.
 28. The method of claim 27 wherein measuring theresistance of the magnetic memory cell comprises: generating an electriccurrent in the word line; and receiving an electric current in themagnetic memory cell.
 29. (canceled)
 30. The method of claim 27 whereingenerating a magnetic field in a first direction around the bit line tothereby align a magnetic polarization within the memory cell comprisesaligning a magnetic polarization within a readout layer in the magneticmemory cell and wherein generating a magnetic field in a seconddirection opposite said first direction around the bit line to therebyreverse the magnetic polarization within the magnetic memory cellcomprises reversing the magnetic polarization within the readout layer.31. A method of reading from a magnetic random access memory (MRAM) witha word line, a magnetic memory cell electrically coupled to the wordline, and a bit line magnetically coupled to, adjacent to andelectrically isolated from the memory cell, the method comprising:measuring the resistance of the magnetic memory cell; generating amagnetic field around the bit line to thereby reverse a magneticallypre-existing polarization within the magnetic memory cell according tothe direction of the magnetic field; and measuring the resistance of thememory cell.
 32. (canceled)
 33. A magnetic random access memory (MRAMwith stackable architecture comprising: a memory cell comprising: astorage layer with high-coercivity configured for storing information; athin insulating layer coupled to the storage layer and configured toform a magnetic tunneling junction (MTJ); and a readout layer withlow-coercivity coupled to the thin insulating layer and configured toprovide a relative readout for determining the magnetization of thestorage layer.
 34. The MRAM of claim 33 wherein the storage and readoutlayers further comprise a plurality of CoPt layers, wherein the numberof CoPt layers determines the relative coercivity between the storageand readout layers.
 35. The MRAM of claim 34 further comprising: a firstbit line magnetically coupled to and electrically isolated from themagnetic memory cell; and a second bit line magnetically coupled to andelectrically isolated from the magnetic memory cell and parallel to thefirst bit line, wherein the first and second bit lines are configured togenerate a magnetic field at the location of the magnetic memory cell byconveying electric current in opposite directions.
 36. The MRAM of claim34 further comprising: a first bit line magnetically coupled to andelectrically isolated from the magnetic memory cell; and a second bitline magnetically coupled to and electrically isolated from the magneticmemory cell and parallel to the first bit line, wherein the first andsecond bit lines are configured to generate a magnetic field at thelocation of the magnetic memory cell by conveying electric current inthe same direction.
 37. The MRAM of claim 36 wherein the magnetic memorycell is between the first and second bit lines.
 38. The MRAM of claim 36further comprising: a cladding layer coupled to the storage layer andconfigured to magnetically couple the first and second bit lines to themagnetic memory cell, wherein the magnetization of the storage layerswitches through anti-parallel magnetic coupling of the storage layerand the cladding layer.
 39. The MRAM of claim 38 further comprising: afirst CuTa layer coupled to the memory cell; a second CuTa layer coupledto the first bit line; and a third CuTa layer coupled to the second bitline, the first, second and third CuTa layers configured to control theresistance of the magnetic memory cell, first and second bit lines. 40.A magnetic random access memory (MRAM) with stacked memory layerscomprising: a substrate; a first memory layer on the substrate andcomprising (a) first plurality of magnetic memory cells aligned in afirst row, each of the first plurality of memory cells separated by aninsulator and electrically isolated from each other and configured tostore information (b) a first conductive bit line parallel to,horizontally disposed from, and electrically isolated from the firstrow, the first bit line configured to select from the first plurality ofmagnetic memory cells, wherein the first bit line is close enough to bemagnetically coupled to the first row; and (c) a second conductive bitline parallel to and electrically isolated from the first row, the firstrow being located between the first and second bit lines, the second bitline configured, in conjunction with the first bit line, to select fromthe first plurality of magnetic memory cells, wherein the second bitline is close enough to be magnetically coupled to the first row; asecond memory layer on the first memory layer and comprising (d) asecond plurality of magnetic memory cells aligned in a second row abovethe first row, each of the second plurality of memory cells separated byan insulator and electrically isolated from each other and configured tostore information, each of the memory cells in the second row beingstacked on and aligned with a corresponding memory cell in theunderlying first row to form a memory cell column on the substrate; (e)a third conductive bit line above the first conductive bit line andparallel to, horizontally disposed from, and electrically isolated fromthe second row, the third bit line being stacked on and aligned with theunderlying first bit line to form a first bit line column on thesubstrate, the third bit line configured to select from the secondplurality of magnetic memory cells, wherein the third bit line is closeenough to be magnetically coupled to the second row; and (f) a fourthconductive bit line above the second conductive bit line and parallel toand electrically isolated from the second row, the second row beinglocated between the third and fourth bit lines, the fourth conductivebit line being stacked on and aligned with the underlying second bitline to form a second bit line column on the substrate, the fourth bitline configured, in conjunction with the third bit line, to select fromthe second plurality of magnetic memory cells, wherein the fourth bitline is close enough to be magnetically coupled to the second row; and aplurality of conductive word lines above the second layer and alignedorthogonal to and electrically isolated from the bit lines, eachconductive word line being electrically coupled to a respective memorycell column. 41-46. (canceled)
 47. A method of manufacturing a magneticrandom access memory (MRAM), comprising: sequentially depositing aseries of layers on a dielectric surface; and thereafter patterning thedeposited layers to simultaneously form a plurality of parallel rows ofmemory cells and a plurality of conductive bit lines parallel to thememory cell rows.